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NT7181
V 2.1
LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface
NT7181 Specification
V 2.1
NOVATEK MICROELECTRONICS CORP.
1
1 2
FEATURES ....................................................................................................................................................................... 3 GENERAL DESCRIPTION ............................................................................................................................................ 3 2.1 BLOCK DIAGRAMS ....................................................................................................................................................... 3
3 4
PIN CONFIGURATION .................................................................................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................. 5 4.1 4.2 RECOMMENDED OPERATING CONDITIONS.................................................................................................................... 5 TIMING REQUIREMENTS ............................................................................................................................................... 5
5 6 7 8 9
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS......................... 6 SWING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS .................................... 7 PARAMETER MEASUREMENT INFORMATION.................................................................................................... 8 APPLICATION INFORMATION ............................................................................................................................... 12 ORDERING INFORMATION ..................................................................................................................................... 14
10 PACKAGE INFORMATION ....................................................................................................................................... 15
2
1 Features
! 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput ! Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI ! 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential ! Operates From a Single 3.3V Supply With 250mW (Typ) ! Low profile 56 Lead TSSOP Package ! Clock edge Programmable for Transmitter ! Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz ! Supports Spread Spectrum Clock Generator ! Suggests to use for LCD monitor only ! No External Components Required for PLL
2 General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for rising edge strobe(RFB=1) or falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN. The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0C to 70C.
2.1 Block Diagrams
NT7181
CMOS / TTL INPUTS
7
DATA (LVDS)
T T L P A R A L L E L | T O | L V D S
T0P T0M T1P T1M T2P T2M
T3P T3M
TD0-6
7
TD7-13
7
TD14-20
(175 Mbit/s To 595 Mbit/s On Each LVDS Cnannel)
TD21-27
7
(TRANSMIT CLOCK IN) (25 MHz To 85 MHz)
PLL
TCLKP TCLKM
POWER DOWN
CLOCK (LVDS) (25 MHz To 85 MHz)
3
3 Pin Configuration
NT7181
VCC TD5 TD6 TD7 GND TD8 TD9 TD10 VCC TD11 TD12 TD13 GND TD14 TD15 TD16 RFB TD17 TD18 TD19 GND TD20 TD21 TD22 TD23 VCC TD24 TD25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 TD4 TD3 TD2 GND TD1 TD0 TD27 LVDSGND T0M T0P T1M T1P LVDSVCC LVDSGND T2M T2P TCLKM TCLKP T3M T3P LVDSGND PLLGND PLLVCC PLLGND PWDN CLKIN TD26 GND
4
4 Absolute Maximum Ratings
Supply voltage range, VCC (see Note1)..............................................................-0.3V to 4V Output voltage range, VO.................................................................................-0.3V to VCC +0.3V Input voltage range, VI...............................................................................................-0.3V to Vcc +0.3V Storage temperature range, Tstg.....................................................................-65C to 150C Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds...........................260C Junction Temperature....................................................................................150C
# Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
4.1 Recommended Operating Conditions
Symbol VCC VIH VIL ZL TA Parameter Supply voltage High-level input voltage Low-level input voltage Differential load impedance Operating free-air temperature 90 0 100 Min. 3.0 2 0.8 110 70 Nom. 3.3 Max. 3.6 Unit V V V C
4.2 Timing requirements Symbol TC tW tT tsu th Cycle time, input clock Pulse duration, high-level input clock Transition, Setup time, data, TD0 - TD27 valid before CLKINor CLKIN (See Figure 1) Hold time, data, , TD0 - TD27 valid after CLKINor CLKIN (See Figure 1) 5 2.5 Parameter Min. 11.8 0.4tc Nom. Max. 40 0.6tc 5 Unit ns ns ns ns ns
Note: th is measured under the conditions of input clock jitter of 1.9ns at 65MHz.
5
5 Electrical Characteristics Over Recommended Operating Conditions
Symbol lVODl Parameter Differential Steady-state Output Voltage Magnitude Change in the Steady-state Differential Output Voltage Magnitude between Opposite binary States Steady-state Common-mode Output Voltage Peak-to-peak Common-mode Output Voltage High-level Input Current Low-level Input Current Short-circuit Output Current 1.125 80 Min. 240 Typ. Max. 490 Unit mV RL = 100, See Figure 2 Test Conditions
IVODI
35
mV
VOC(SS) VOC(PP) IIH IIL IOS
1.475 150 20 30 24 12
V See Figure 2 mV A A mA mA A uA VIH = VCC VIL = 0 VO(TP) = 0 VOD = 0 VO = 0 to Vcc Disables, All inputs at GND Enables, RL = 100, Gray-scale pattern (see Figure 3), VCC = 3.3V, tc = 15.38ns Enabled, RL = 100, (4 places) Worst-case pattern (see Figure 4), tc = 15.38ns
IOZ
High-impedance State Output Current
1 280
68 ICC Quiescent Supply Current
80
mA
75
110
mA
*All typical values are at VCC = 3.3V, TA = 25C
6
6 Swing Characteristics Over Recommended Operating Conditions
Symbol td0 td1 td2 td3 td4 td5 td6 Parameter Delay Time, TCLK to Serial Bit Position 0 Delay Time, TCLK to Serial Bit Position 1 Delay Time, TCLK to Serial Bit Position 2 Delay Time, TCLK to Serial Bit Position 3 Delay Time, TCLK to Serial Bit Position 4 Delay Time, TCLK to Serial Bit Position 5 Delay Time, TCLK to Serial Bit Position 6 Min. -0.4 1.8 4.0 6.2 8.4 10.6 12.8 Typ.* Max. 0.3 2.5 ns 4.7 ns 6.9 ns 9.1 ns 11.3 ns 13.5 ns tc = 15.38 ns ( 0.2%), |Input Clock Jitter| < 50 ps** See Figure 5 tc = 15.38 ns ( 0.2%), |Input Clock Jitter| < 50 ps ** See Figure 5 Unit ns Conditions
td7
Delay Time, CLKIN or CLKIN to TCLK
3.0
4.2
5.5
ns
tw tt ten tdis
Pulse Duration, High-Level Output Clock Transition Time, Differential Output Voltage (tr or tf) Enable Time, PWDN to Phase Lock (TCLK Valid) Disable Time, PWDN to Off State (TCLK Low)
0.35tc 260
4 tc 7
0.65tc 1500 10 100
ns ps ms ns See Figure 2 See Figure 6 See Figure 7
700
* All typical values are at VCC = 3.3V, TA = 25C ** |Input Clock Jitter| is the magnitude of the change in the input clock period.
7
7 Parameter Measurement Information
tsu TDn
th
CLKIN (RFB=0) CLKIN (RFB=1)
Note A: All input timing is defined at 1.4V on an input signal with a 10%-to-90% rise or fall time of less than 5ns.
Figure 1. Setup and Hold Time Definition
TP
49.9 1% (2 Places)
VOD
TM CL = 10 pF Max (2 Places)
Voc
(a) SCHEMATIC
100% 80%
VOD(H)
0V
VOD(L)
20% 0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0V
(b) WAVEFORMS Figure 2. Test Load and Voltage Definitions for VLDS Outputs
8
CLKIN TD0, 8, 16 TD1, 9, 17 TD2, 10, 18 TD3, 11, 19
TD24 - 27 All others
Notes:
A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2V and VIL = 0.8V.
Figure 3. 16-Grayscale Test-Pattern Waveforms
tc CLKIN Even TDn Odd TDn
Notes: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. B. VIH = 2V and VIL = 0.8V. Figure 4. Worst-Case Test-Pattern Waveforms
9
CLKIN (RFB=0) CLKIN (RFB=1)
td7
TCLK
td0 Tn
TD7
TD6
td1
TD4
TD3
TD2
TD1
TD0
TD7+1
TD6+1
td2 td3 td4 td5 td6
2.5V CLKIN 1.4V 0.5V td7 TCLK or Tn
VOD(H) 0.00V VOD(L) td0 - td6
Figure 5. Timing Definitions
10

CLKIN TDn
ten
PWDN TCLK
Invalid
Valid
Figure 6. Enable Time Waveforms
CLKIN tdis PWDN
TCLK
Figure 7. Disable Time Waveforms
11
8 Application Information
Host Cable Flat Panel Dispaly
Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA
NA
18-BIT RED0 RED1 RED2 RED3 RED4 RED5
NA NA
24-BIT RED0 RED1 RED2 RED3 RED4 RED5
RED6 RED7
NT7181
THC63LVDF84A
48
51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24
D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21
T0M
9 100
A1M
T0P
47
10
A1P
T1M
46
11 100
A2M
GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD
NA NA BLUE0
GREEN0 GREEN0 GREEN1 GREEN1 GREEN2 GREEN2 GREEN3 GREEN3 GREEN4 GREEN4 GREEN5 GREEN5
NA NA BLUE0 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6
T1P
45
12 A2P
T2M
42
15 100
A3M
T2P
41
16
A3P
BLUE1 BLUE2 BLUE3 RSVD RSVD
NA NA H_SYNC
BLUE1 BLUE2 BLUE3 BLUE4 BLUE5
NA
T3M
38
19 100
A4M
NA BLUE7 H_SYNC H_SYNC
D22 16 D16 18 D17 27 D24 28 D25 30 D26 25 D23 31 CLKIN
T3P
37
20
A4P
TCLKM
40
17
CLKINM
V_SYNC ENABLE
NA CLOCK
V_SYNC V_SYNC ENABLE ENABLE
NA CLOCK RSVD CLOCK
100
TCLKP 39 18 CLKINP
Figure 12. Color Host to LCD Panel Application
12
Host
Cable
Flat Panel Dispaly
Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA
NA
18-BIT RED0 RED1 RED2 RED3 RED4 RED5
NA NA
24-BIT RED0 RED1 RED2 RED3 RED4 RED5
RED6 RED7
NT7181
DS90CF386
48
51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24
D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21
D22
T0M
9 100
RxIN0-
T0P
47
10
RxIN0+
T1M
46
11 100
RxIN1-
GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD
NA NA BLUE0
GREEN0 GREEN0 GREEN1 GREEN1 GREEN2 GREEN2 GREEN3 GREEN3 GREEN4 GREEN4 GREEN5 GREEN5
NA NA BLUE0 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6
T1P
45
12
RxIN1+
T2M
42
15 100
RxIN2-
T2P
41
16
RxIN2+
BLUE1 BLUE2 BLUE3 RSVD RSVD
NA NA H_SYNC
BLUE1 BLUE2 BLUE3 BLUE4 BLUE5
NA
T3M
38
19 100
RxIN3-
T3P
37
20
RxIN3+
NA BLUE7 H_SYNC H_SYNC
16 D16 18 D17 27 D24 28 D25 30 D26 25 D23 31 CLKIN
TCLKM
40
17
RxCLKIN-
V_SYNC ENABLE
NA CLOCK
V_SYNC V_SYNC ENABLE ENABLE
NA CLOCK RSVD CLOCK
100
TCLKP 39 18 RxCLKIN+
Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application*
13
9 Ordering Information
Part No. NT7181F NT7181FQ Package 56L TSSOP 56L TSSOP Packing Tube Tape on reel
14
10 Package Information
TSSOP 56L Outline Dimensions
unit : inches/mm
15

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